1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a semiconductor device that can be applied in system on chip (SOC).
2. Description of Related Art
In order to fulfill the requirements of lightness, small sizes and multi-functions, fabrication of integrated circuits (ICs) has moved toward system on chip (SOC). That is fabricating read only memory (ROM), static random access memory (SRAM), flash memory or dynamic random access memory (DRAM), together with logic circuits and digital circuits on a single chip.
However, for one single chip including DRAM, flash memory, logic circuits and radio frequency (RF) devices, it is very complicated to design the circuit layout for electrical connection. Furthermore, different fabricating methods are required for devices with different functions. Therefore, it is important to integrate fabricating processes for different devices located on a SOC chip.
FIG. 1 shows the top view for a memory cell region of the prior art SOC chip. FIG. 2 illustrates the cross-sectional view of the prior art SOC chip. As shown in FIG. 2, there are a memory cell region 200 and a peripheral circuit region 202. The memory cell region 200a is the cross-sectional view along line I-Ixe2x80x2 in FIG. 1, while the memory cell region 200b is the cross-sectional view along line II-IIxe2x80x2 in FIG. 1.
Referring to FIGS. 1 and 2, a substrate 100 is provided with a memory cell region 200 and a peripheral circuit region 202. In the memory cell region 200, a plurality of bit-lines 102 are formed on the substrate, together with a composite dielectric layer 104, for example, an oxide/nitride/oxide layer, a plurality of gates 108, an anti-punch through region 114 and spacers 116 on sidewalls of the gates 108. In the peripheral circuit region 202, a dielectric layer 106 is formed on the substrate in a PMOS device region within the peripheral circuit region 202, together with a plurality of gates 110, P type lightly doped drains (LDD) 112, source/drain regions 120 and spacers 118 on sidewalls of the gate 110.
In the manufacture processes for the above SOC chip, anisotropic etching is used to removed a portion of the dielectric layer (not shown) in order to form the spacers 116, 118 on the sidewalls of the gates 108, 110. However, over etching occurs in the surface of the substrate in the memory cell region, thus forming silicon recesses 122. Because the surface of the substrate has a higher dopant concentration, silicon recesses result in dopant concentration minus. Therefore, punch-through can happen in the substrate along with silicon recesses, due to dopant concentration minus. As a result, P type ions have to be implanted with high energy to form LDD 112 in the PMOS device region within the peripheral circuit region 202 and anti-punch through regions 114 in the memory cell region 200, at the same time. However, after forming anti-punch through regions 114 in the memory cell region 200, the threshold voltage (Vt) is increased and junction breakdown occurs in the source/drain junction due to diffusion of P-type ions.
The present invention provides a method for fabricating a semiconductor device that can be applied in system on chip (SOC). The present invention can avoid forming silicon recesses in the memory cell region, so that no anti-punch through implantation is required, thus enhancing device performance.
The present invention provides a method for fabricating a semiconductor device that can be applied in system on chip (SOC), comprising providing a substrate with a memory cell region and a peripheral circuit region; forming a plurality of bit-lines in the memory cell region; forming a first and a second dielectric layers respectively in the memory cell region and the peripheral circuit region; and forming a plurality of gates in the memory cell region and the peripheral circuit region. Next, a blanket ion implantation step is performed to form a plurality of P type LDDs in the substrate besides the gates in a PMOS device region within the peripheral circuit region. The blanket ion implantation step is performed with an energy that is high enough to form P type LDDs in the peripheral circuit region without forming an anti-punch through region in the substrate of the memory cell region. Afterwards, a plurality of spacers are formed on sidewalls of the gates. The spacers formed on the sidewalls of the gates in the memory cell region are connected to one another. An ion implantation step is performed to form a plurality of P type source/drain regions in the substrate besides the gates in the PMOS device region within the peripheral circuit region.
As embodied and broadly described herein, the invention can prevent over-etching in the substrate between the gates in the memory cell region. As the integration of the device increases, the spacers on the sidewalls of the gates connect to one another due to decreased distance between the gates in the memory cell region. Because of protection from the connected spacers, over etching can be prevented, further avoiding silicon recesses. As a result, no anti-punch through implantation is required for the silicon recesses in the memory cell region.
Furthermore, during the ion implantation step for forming P type LDDs in the PMOS device region within the peripheral circuit region, an energy level that is high enough is used to penetrate the surface of the substrate in the PMOS device region within the peripheral circuit region, without penetrating the surface of the substrate in the memory cell region. Therefore, only P type LDDs in the peripheral circuit region are formed, but not forming the anti-punch through region in the memory cell region. As a result, the increased threshold voltage (Vt) and junction breakdown in the source/drain junction due to diffusion of P-type ions can be prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.